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june 2011 doc id 17728 rev 3 1/51 51 STPM10 programmable single-phase energy metering ic with tamper detection features measures active, reactive, and apparent energies current, voltage rms and instantaneous measurement frequency measurement ripple-free active energy pulsed output live and neutral monitoring for tamper detection fast and simple one-point digital calibration over the whole current range integrated linear voltage regulators for digital and analog supply selectable rc or crystal oscillator supports 50 - 60 hz - iec62052-11, iec62053- 2x specifications less than 0.1% error in the 1000:1 range precision voltage reference: 1.23 v with 30 ppm/c max description the STPM10 is designed for effective measurement of active, reactive and apparent energy in a power line system using current transformer and shunt sensors. the device can be implemented for peripheral measurement in a microcontroller-based single-phase or poly-phase energy meter. the STPM10 consists of two main sections: analog and digital. the analog part is composed of preamplifier and first-order sigma- delta a/d converter blocks, a band-gap voltage reference and low-drop voltage regulator. the digital part is composed of system control, oscillator, hard-wired dsp and spi interface. there is also an internal volatile memory, which is controlled through the spi by means of a dedicated command set. the configured bits are used for configuration and calibration purposes. from a pair of sigma-delta output signals produced by the analog section, the dsp unit computes the amount of active, reactive and apparent energy consumed, as well as the rms and instantaneous voltage and current values. the results of the computation are available as pulse frequencies and states on the digital outputs of the device, or as data bits in a data stream, which can be read from the device by means of the spi interface. the system bus interface is also used for temporary programming of bits of internal volatile memory. the STPM10 generates an output signal with a pulse frequency proportional to the energy, and this signal is used in the calibration phase of the energy metering application. tssop20 table 1. device summary order code temperature range package packaging STPM10btr - 40 to 85 c tssop20 (tape and reel) 2500 parts per reel www.st.com
contents STPM10 2/51 doc id 17728 rev 3 contents 1 schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 measurement error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 adc offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 power supply dc and ac rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.5 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 general operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 ? a/d converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 zero-crossing detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 period and line voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.6 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.7 load monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.8 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.9 tamper detection module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.9.1 detailed operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.10 phase compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.11 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.11.1 rc startup procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.12 resetting the STPM10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.13 using the STPM10 in microcontroller-based meters . . . . . . . . . . . . . . . . 24
STPM10 contents doc id 17728 rev 3 3/51 7.14 energy to frequency conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.15 status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.16 programming the STPM10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.16.1 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.17 configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.18 mode signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.19 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.20 remote reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.21 reading data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.22 writing procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.22.1 interfacing the standard 3-wire spi with the STPM10 spi . . . . . . . . . . 36 7.23 energy calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.23.1 active power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.23.2 reactive power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.23.3 apparent power and rms values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.24 STPM10 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8 application design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
list of tables STPM10 4/51 doc id 17728 rev 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. gain of voltage and current channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 table 7. configuration of current sensors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. no-load detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. led pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. status bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. configuration bit map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. mode signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. working point settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14. device constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15. resistor divider ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 16. current channel typical components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 table 17. footprint data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STPM10 list of figures doc id 17728 rev 3 5/51 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. supply current vs. supply voltage, t a = 25 c (f = 4.194 mhz, 8.192 mhz). . . . . . . . . . . . 13 figure 4. rc oscillator frequency vs. v cc , r = 12 k , t a = 25 c . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. rc oscillator: frequency jitter vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. analog voltage regulator: line - load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. digital voltage regulator: line - load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. voltage channel linearity at different v cc voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. power supply ac rejection vs. v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. power supply dc rejection vs. v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 11. error over dynamic range gain dependence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 12. primary current channel linearity at different v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 13. gain response of ? a/d converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 14. first-order ? a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15. zcr signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 16. lin and bfr signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 17. band-gap temperature variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 18. timings of tamper module - primary channel selected. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 19. timings of tamper module - secondary channel selected . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 20. different oscillato r circuits with (a) quartz, (b ) internal oscillator, (c) external source . . . . . 23 figure 21. STPM10 data records map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 22. timing for providing remote reset request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 figure 23. data record reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 24. timing for data record reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 25. timing for writing configuration and mode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 26. active energy computation diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 27. STPM10 reference schematic with one current transformer and one shunt. . . . . . . . . . . . 45 figure 28. tssop20 footprint recommended data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
schematic diagram STPM10 6/51 doc id 17728 rev 3 1 schematic diagram figure 1. block diagram vdda vddd vo led wdg zcr s da/td s yn s c s s cl/nc clkout clkin v ss iin2 iip2 iin1 iipi vin vip vcc volt a ge ref line a r vreg s 56- b it config u r a tor s d s p energie s a nd rm s v a l u e s energy to fre q converter s regi s ter s a nd s pi interf a ce o s cill a tor ? a/d + - g a in: 8 - 3 2 t a mper + - + - ? a/d g a in: 8 - 3 2 4 am00176v1
STPM10 pin configuration doc id 17728 rev 3 7/51 2 pin configuration figure 2. pin connections (top view) table 2. pin description pin symbol type (1) description 1 wdg d o watchdog 2 zcr d o zero-crossing signal 3 scs d in spi interface enable pin 4v ddd a out 1.8 v output of internal low drop regulator which supplies the digital core 5v ss gnd ground 6v cc p in supply voltage 7v o p out output of internal low drop regulator 8v dda a out 3 v output of internal low drop regulator which supplies the analog part 9i ip1 a in positive input of primary current channel 10 i in1 a in negative input of primary current channel 11 i ip2 a in positive input of secondary current channel 12 i in2 a in negative input of secondary current channel 13 v ip a in positive input of voltage channel 14 v in a in negative input of voltage channel 15 syn d i/o spi interface pin 16 clkin a in crystal oscillator input 17 clkout a out crystal oscillator output 18 scl d i/o spi interface clock pin 19 sda d i/o spi interface data pin 20 led d o active energy pulsed output 1. a: analog, d: digital, p: power
maximum ratings STPM10 8/51 doc id 17728 rev 3 3 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these condition is not implied. table 3. absolute maximum ratings symbol parameter value unit v cc dc input voltage -0.3 to 6 v i pin current on any pin (sink/source) 150 ma v id input voltage at digital pins (scs, zcr, wdg, syn, sda, scl, led) -0.3 to v cc + 0.3 v v ia input voltage at analog pins (i ip1 , i in1 , i ip2 , i in2 , v ip , v in ) -0.7 to 0.7 v esd human body model (all pins) 3.5 kv t op operating ambient temperature - 40 to 85 c t j junction temperature - 40 to 150 c t stg storage temperature range - 55 to 150 c table 4. thermal data symbol parameter value unit r thja thermal resistance junction-to-ambient 114.5 (1) c/w 1. this value is based on a single-l ayer pcb, jedec standard test board.
STPM10 electrical characteristics doc id 17728 rev 3 9/51 4 electrical characteristics v cc = 5 v, t a = 25 c,100 nf to 1 f between v dda and v ss , 100 nf to 1 f between v ddd and v ss , 100 nf to 1 f between v cc and v ss unless otherwise specified. table 5. electrical characteristics symbol parameter test conditions min. typ. max. unit energy measurement accuracy f bw effective bandwidth limited by digital filtering (-3 db) 4 800 hz e aw accuracy of active power over 1 to 1000 of dynamic range 0.1 % e rw accuracy of reactive power over 1 to 1000 of dynamic range 0.1 % e sw accuracy of apparent power over 1 to 500 of dynamic range 0.1 % snr signal-to-noise ratio over the entire bandwidth 52 db psrr dc power supply dc rejection voltage signal: 200 mv rms /50hz current signal: 10 mv rms /50hz f clk = 4.194 mhz v cc =3.3v10%, 5v10% 0.2 % psrr ac power supply ac rejection voltage signal: 200 mv rms /50 hz current signal: 10 mv rms /50 hz f clk = 4.194 mhz v cc =3.3 v+0.2 v rms 1@100 hz v cc =5.0 v+0.2 v rms 1@100 hz 0.1 % general section v cc operating supply voltage 3.165 5.5 v i cc supply current. configuration registers cleared 4 mhz; v cc =5 v 3 4 ma 8 mhz; v cc =5 v 5 6 ma por power on reset on v cc 2.5 v v dda analog supply voltage 2.85 3.00 3.15 v v ddd digital supply voltage 1.725 1.80 1.875 v f clk oscillator clock frequency mdiv bit=0 4.000 4.194 mhz mdiv bit=1 8.000 8.192 mhz f line nominal line frequency 45 65 hz i latch current injection latch-up immunity 300 ma analog inputs (i ip1 , i in1 , i ip2 , i in2 , v ip , v in ) v max maximum input signal levels voltage channel -0.3 +0.3 v current channels: gain 8x -0.15 +0.15 v gain 32x -0.035 +0.035 f adc a/d converter bandwidth 10 khz f spl a/d sampling frequency f clk /4 hz
electrical characteristics STPM10 10/51 doc id 17728 rev 3 symbol parameter test conditions min. typ. max. unit v off amplifier offset 20 mv z ip v ip , v in impedance over the total operating voltage range 100 400 k z in i ip1 , i in1 , i ip2 , i in2 impedance over the total operating voltage range 100 k g err current channels gain error 10 % i vl voltage channel leakage current -1 1 a i il current channel leakage current channel disabled (pst=0 to 1 ch2 disabled if csel=0; ch1 disabled if csel=1) or device off -1 1 a input enabled -10 10 a digital i/o characteristics (sda , clkin, clkout, scs, syn, led) v ih input high voltage sda, scs, syn, led 0.75v cc v clkin 1.5 v il input low voltage sda, scl, syn, led 0.25v cc v clkin 0.8 v oh output high voltage i o =-2 ma v cc -0.4 v v ol output low voltage i o =+2 ma 0.4 v i up pull up current 15 a t tr transition time c load =50 pf 10 ns crystal oscillator (see circuit figure 19) i i input current on clkin 1 a r p external resistor 1 4 m cp external capacitors 22 pf f clk nominal output frequency 4.00 4.194 mhz 8.00 8.192 i clkin settling current f clk = 4 mhz 40 60 a r set settling resistor 12 k t jit frequency jitter 1 ns on chip reference voltage v ref reference voltage 1.23 v reference accuracy 1 % t c temperature coefficient after calibration 30 50 ppm/ c spi interf ace timing f sclkr data read speed after calibration 32 mhz table 5. electrical characteristics (continued)
STPM10 electrical characteristics doc id 17728 rev 3 11/51 symbol parameter test conditions min. typ. max. unit f sclkw data write speed 100 khz t ds data setup time 20 ns t dh data hold time 0 ns t on data driver on time 20 ns t off data driver off time 20 ns t syn syn active width 2/f clk s table 5. electrical characteristics (continued)
terminology STPM10 12/51 doc id 17728 rev 3 5 terminology 5.1 measurement error the error associated with the energy measurement made by the STPM10 is defined as: percentage error = [STPM10 (reading) - true energy] / true energy 5.2 adc offset error this is the error due to the dc component associated with the analog inputs of the a/d converters. due to the internal automatic dc offset cancellation, the STPM10 measurement is not affected by dc components in the voltage and current channel. the dc offset cancellation is implemented in the dsp. 5.3 gain error the gain error is gain due to the signal channel gain amplifiers. this is the difference between the measured adc code and the ideal output code. the difference is expressed as percentage of the ideal code. 5.4 power supply dc and ac rejection this parameter quantifies the STPM10 measurement error as a percentage of the reading when the power supplies are varied. for the psrrac measurement, a reading at two nominal supply voltages (3.3 and 5 v) is taken. a second reading is obtained with the same input signal levels when an ac (200 mv rms /100 hz) signal is introduced on the supplies. any error introduced by this ac signal is expressed as a percentage of the reading. for the psrrdc measurement, a reading at two nominal supply voltages (3.3 and 5 v) is taken. a second reading is obtained with the same input signal levels when the supplies are varied 10%. any error introduced is again expressed as a percentage of the reading. 5.5 conventions the lowest analog and digital power supply voltage is called vss, which represents system ground (gnd). all voltage specifications for digital input/output pins are referred to gnd. positive currents flow into a pin. sinking current refers to the current flowing into the pin, and thus it is positive. sourcing current means that the current is flowing out of the pin, so it is negative. timing specifications of signals treated by the digital control part are relative to clkout. this signal is provided by the 4.194 mhz nominal- frequency crystal oscillator or from the internal rc oscillator. an external source of 4.194 mhz or 8.192 mhz can also be used. timing specifications of signals from the spi interface are relative to the scl, and there is no direct relationship between the clock (scl) of the spi interface and the clock of the dsp block. a positive logic convention is used in all equations.
STPM10 typical performance characteristics doc id 17728 rev 3 13/51 6 typical performance characteristics figure 3. supply current vs. supply voltage, t a = 25 c (f = 4.194mhz, 8.192mhz) figure 4. rc oscillator frequency vs. v cc , r = 12 k , t a = 25 c figure 5. rc oscillator: frequency jitter vs. temperature figure 6. analog voltage regulator: line - load regulation figure 7. digital voltage regulator: line - load regulation figure 8. voltage channel linearity at different v cc voltages
typical performance characteristics STPM10 14/51 doc id 17728 rev 3 figure 9. power supply ac rejection vs. v cc figure 10. power supply dc rejection vs. v cc figure 11. error over dynamic range gain dependence figure 12. primary current channel linearity at different v cc figure 13. gain response of ? a/d converters
STPM10 theory of operation doc id 17728 rev 3 15/51 7 theory of operation 7.1 general operation description the STPM10 is capable of performing measurements of active, reactive and apparent energy, rms and instantaneous voltage and current values, and line frequency information. most of the functions are fully programmable using internal configuration bits accessible through the spi interface. the STPM10 works as a peripheral in microcontroller-based metering systems. the zcr and wdg pins are used to provide zero-crossing and watch- dog information, and the spi pins are used to communicate with the microcontroller. the STPM10 includes volatile internal registers that hold the useful information for the metering system. two kinds of active energy are available: wide-ban d active energy (aw) which includes all harmonic content (also called type 0) and fundamental active energy (af), limited to the 1st harmonic (also called type 1). this latter energy value is obtained by filtering type 0 active energy. both the two active energies are stored in up-down counting accumulator registers with a 20-bit length. reactive and apparent energies are also available with a 20-bit accumulation. the STPM10 also provides the rms values for voltage and current. due to the modest dynamic variation of the voltage, the rms value is stored with a resolution of 11 bits, while the rms current value has a resolution of 16 bits. the instantaneous (momentary) sampled value of voltage and current are also available with a resolution of 11 and 16 bits, respectively. the line frequency value is stored with a resolution of 14 bits. due to the proprietary energy computation algorithm, the STPM10 calibration is quick and simple, allowing calibration at only one point over the entire current range. the configuration and calibration parameters must be downloaded in the internal non- volatile memory of STPM10 at power-up. 7.2 analog inputs input amplifiers the STPM10 has one fully differential voltage input channel and two fully differential current input channels. the voltage channel consists of a differential amplifier with a gain of 4. the maximum differential input voltage for the voltage channel is 0.3 v. the two current channels are multiplexed (see chapter 7.9 for details) to provide a single input to a preamplifier with a gain of 4. the output of this preamplifier is connected to the input of a programmable gain amplifier (pga) with possible gain selections of 2 and 8. the total gain of the current channels are then 8 and 32. the gain selections are made by writing to the gain register, and they can be different for the two current channels. if the tamper function is not used, the secondary current can be disabled. the maximum differential input voltage is dependent on the selected gain, in accordance with ta bl e 6 .
theory of operation STPM10 16/51 doc id 17728 rev 3 the gain register is included in the device configuration register with the address name pst. the table below shows the gain configuration according to the register values: note: if the device is used in configuration pst = 1, tmp = 1 (primary channel with ct, secondary channel with shunt), the shunt ks must always be equal to one fourth of the current transformer ks. both the voltage and current channels implement an active offset correction architecture which provides the benefit of avoiding any offset compensation.the analog voltage and current signals are processed by the analog-to-digital converters, which feed the hard- wired dsp. the dsp implements an automatic digital offset cancellation that makes it possible to avoid any manual offset calibration on the analog inputs. 7.3 ? a/d converters analog-to-digital conversion in the STPM10 is carried out using two first-order converters. the device performs a/d conversi ons of analog signals on two independent channels in parallel. the current channel is multiplexed as a primary or secondary current channel in order to perform the tamper function, if enabled. the converted signals are supplied to the internal hard-wired dsp unit, which filters and integrates these signals in order to boost the resolution and to yield all the necessary signals for the computations. a modulator converts the input signal into a continuous serial stream of 1?s and 0?s at a rate determined by the sampling clock. in the STPM10, the sampling clock is equal to f clk /4. the 1-bit dac in the feedback loop is driven by the serial data stream. the dac output is subtracted from the input signal. if the loop gain is high enough, the average value of the dac output (and therefore the bit stream) can approach that of the input signal level. when a large number of samples are averaged, a ve ry precise value for the analog signal is obtained. this averaging is carried out in th e dsp section, which implements decimation, table 6. gain of voltage and current channels voltage channels current channels gain max input voltage (v) gain max input voltage (v) 4 0.30 8x 0.15 32x 0.035 table 7. configuration of current sensors primary secondary configuration bits configuration bits gain sensor gain sensor pst tmp 8 ct disabled disabled 0 0 32 shunt disabled disabled 1 0 8 ct 8ct0 1 8 32 shunt 1 1
STPM10 theory of operation doc id 17728 rev 3 17/51 integration and dc offset cancellation of the supplied signals. the gain of the decimation filters is 1.004 for the voltage channel and 0.502 for the current channel. the resulting signal has a resolution of 11 bits per voltage channel and 16 bits per current channel. 7.4 zero-crossing detection the STPM10 has a zero-crossing detector circuit on the voltage channel which can be used by application for synchronization of some utilit y equipment in the even t of zero-crossing of the line voltage. this circuit produces the inte rnal signal zcr which has a rising edge every time the line voltage crosses zero, and a negative edge every time the voltage reaches its positive or negative peak. the zcr signal is then at twice the line voltage frequency. the zcr signal is available on the zcr pin. figure 14. first-order ? a/d converter dac - + integrator f clk /4 input analog signal output digital signal figure 15. zcr signal
theory of operation STPM10 18/51 doc id 17728 rev 3 7.5 period and line voltage measurement the period module measures the period of the base frequency of the voltage channel and checks if the voltage signal frequency is within the f clk /2 17 to f clk /2 15 band. to do this, the lin signal is produced, which is low when the line voltage is rising, and high when the line voltage is falling. this means that the lin signal is the sign of dv/dt. with further elaboration, the zcr signal is also produced. on the tr ailing edge of lin (lin e frequency) the period counter starts counting up pulses of the f clk /4 reference signal. the lin signal is available on the status bit register (see ta bl e 1 0 ). if the counted number of pulses between tw o trailing edges of lin is higher than 2 15 , or if the counting is never stopped (no lin trailing edge) this means that the base frequency is lower than f clk /2 17 hz and a bfr (base frequency range) error flag is set. if the number of pulses counted between tw o trailing edges of lin is lower than 2 13 , the base frequency exceeds the limit (this means it is higher than f clk /2 15 ). in this case, the error must be repeated three consecutive times in order to set the bfr error flag. for example, with a 4.194304 mh z oscillator frequency and md iv bit clear (or 8.192 mhz with mdiv set), f clk /4 is 1.048576 mhz. if the line frequency is 30 hz, the counted f clk /4 pulses between two lin trailing edg es are 34952, more than 2 15 (32768 pulses). the bfr low frequency limit is then: f clk /2 17 = 4194304/131072 = 32 hz figure 16. lin and bfr signals
STPM10 theory of operation doc id 17728 rev 3 19/51 with the same clock frequency, if the line frequency is 130 hz, the f clk /4 pulses between two lin trailing edges ar e 8066, less than 2 13 (8192). the bfr high frequency limit is then: f clk /2 15 = 4194304/32768 = 128 hz. the bfr flag is also set if the register value of the rms voltage drops below 64. bfr is cleared when the register value goes above 128. the bfr, then, also gives information about the presence of the line voltage within the meter. when the bfr error is set, the computation of power is zero unless the frs bit is set. in fact, the effect of the bfr bit can be overridden by setting frs configuration bit. it means that if frs is set and bfr is also set, all the energy computation is carried on as bfr was cleared. in this case then p=u*i, where u could be zero or not (if bfr was set because voltage rms register value is below 64). when the line frequency re-enters the nominal band, the bfr flag is automatically reset. this bfr error flag is also assembled as part of the 8-bit status register (see ta bl e 1 0 ). 7.6 power supply the main STPM10 supply pin is the vcc pin. from the vcc pin two linear regulators provide the necessary voltage for the analog part vdda (3 v) and for the digital part vddd (1.8 v). the vss pin represents the reference point for all the inter nal signals. a 100 nf low esr capacitor should be connected between vcc and vss, vdda and vss, vddd and vss. all these capacitors must be located very close to the device. the STPM10 contains a power on reset (por) detection circuit. if the vcc supply is less than 2.5 v, then the STPM10 goes into an inactive state, all the functions are blocked and a reset condition is asserted. this is useful to ensure correct device operation at power-up and during power-down. the power supply monitor has built-in hysteresis and filtering, which give a high degree of immunity from false triggering due to noisy supplies. a band-gap voltage reference (vbg) of 1.23 v 1% is used as the reference voltage level source for the two linear regulators and for the a/d converters. also, this module produces several bias currents and voltages for all other analog modules. the band-gap voltage can be compensated regardless of the temperature variations with the bgtc bits. figure 17. band-gap temperature variation 1,20 1,21 1,22 1,23 1,24 1,25 1,26 1,27 1,28 1,29 -40 0 40 80 temperature c vbg bgtc=0 bgtc=1 bgtc=2 bgtc=3 100 1,20 1,21 1,22 1,23 1,24 1,25 1,26 1,27 1,28 1,29 -40 0 40 80 temperature c vbg bgtc=0 bgtc=1 bgtc=2 bgtc=3 100
theory of operation STPM10 20/51 doc id 17728 rev 3 7.7 load monitoring the STPM10 includes a no-load condition detection circuit with adjustable threshold. this circuit monitors the voltage and the current channels and, when the measured voltage is below the set threshold, the internal signal bil becomes high. information about this signal is also available in the status bit bil. the no-load condition occurs when the product of the vrms and irms register values is below a given value. this value can be set with the ltch configuration bits. four different no-load threshold values can be chosen according to the two configuration bits ltch (see ta bl e 8 ). when a no-load condition occurs (bil=1) the integration of power is suspended and the tamper module is disabled. the bil signal can be accessed only through the spi interface. 7.8 error detection in addition to the no-load condition and the line frequency band, the integration of power can also be suspended due to an error detected on the source signals. there are two kinds of error-detection circuits involved. the first checks all the signals from the analog part if any is stacked at 1 or 0 within the 1/128 of f clk period of observation. in case of a detected error, the corresponding signal is replaced with an idle signal, which represents a constant value of 0. all error and other resolved flags are treated as bits of a device status and can be read out by means of the spi interface. another error condition occurs if led pin output signals are different from the internal signals that drive them. this can occur if some of these pins are forced to gnd or to some other imposed voltage value. in this case, the internal status bit pin is activated, providing the information that some hardware problem has been detected. 7.9 tamper detection module the STPM10 is able to measure the current in both live and neutral wire with a time domain multiplexing approach on a unique sigma delta modulator. this mechanism is adopted to implement anti-tamper function. if this function is selected (see ta b l e 7 ), the live and neutral wire currents are monitored; when the difference between the two measurements exceeds a rated threshold the STPM10 enters the "tamper state", while in "normal state" the two measurements are below the threshold. in particular, both channels are not observed all the time, rather a time multiplex mechanism is used. during the observation time of each channel, its active energy is calculated. a tamper condition occurs when the absolute va lue of the difference between the two active table 8. no-load detection thresholds ltch k lt ch 0800 1 1600 2 3200 3 6400
STPM10 theory of operation doc id 17728 rev 3 21/51 energy values is greater than a certain percentage of the averaged energy during the activated tamper module (see equation 1 ). this percentage value can be selected between two different values (12.5 % and 6.25 %) according to the value of the configuration bit crit. the tamper condition is detected when the following formula is satisfied: equation 1 energych1 - energych2 > k crit (energych1 + energych2)/2; where k crit can be 12.5 % or 6.25 %. the detection threshold is much higher than the accuracy difference of the current channels, which should be less than 0.2 %, but, some headroom should be left for possible transition effect, due to accidental synchronism of actual load current change with the rhythm of taking the energy samples. the tamper circuit works if the energies associated with the two current channels are both positive or negative, if the two energies have different sign, the tamper is on all the time however, the channel with the associated higher power is selected for the final computation of energy. when internal signals are not good enough to perform the calculations, i.e. line period is out or range or ? signals from analog section are stacked at high or low logic level, or no load condition is activated, the tamper module is disabled and its state is preset to normal. 7.9.1 detailed operat ional description the meter is initially se t to normal state, i.e. tamper not detected.in this condition the primary channel is selected for final integration of energy. in such state the values of both load currents should not differ more than the accuracy difference of the channels does. sixty-four periods of line voltage is used as a tamper checking period. after 24 periods of line voltage two internal signals mux and inh are changed in order to enable secondary current channel and to freeze the last power and rms values of primary current channel. the following 16 periods of line frequency are used for tamper detection integration. during this gap, the final energy calculation does not use the signal from selected channel but the frozen values. four line periods after the inh switch, the integration of power from secondary current channel is started and lasts four periods. additional four line periods later mux signal is switched back to primary current channel and the integration for tamper detection is started. the timings of mux and inh signals are shown in figure 18 below. figure 18. timings of tamper module - primary channel selected mux ch ? 1ch ? 2ch ? 1ch ? 1 inh tamper ? power ? integrators b a cycles 4444 24 24
theory of operation STPM10 22/51 doc id 17728 rev 3 when the secondary channel is selected to be integrated by the final energy integrator, the mux and inh signals change according to figure 19 below. this means that energy of four periods from secondary channel followed by energy of four periods from primary channel is sampled within the tamper module. from these two samples, called b and a respectively, the criteria of tamper is calculated and the channel with higher current is selected, resulting in a new tamper state. if four consecutive new results of criteria happen, i.e. after elapsed 5.12 s at 50 hz , the meter will enter into tamper state. thus, the ch annel with the higher curr ent will be selected for th e energy calculation. if samples of power a and b would have different signs, the tamper would be on all the time but, the channel with bigger power would be still selected for the final integration of energy. if a tamper status has been de tected, the multiplex ratio will be 56:8 if the primary channel energy is greater than the seco ndary one, otherwise it will be 8:56. the detected tamper condition is stored in the bit status bit. if bit = 0 tamper is not detected, if bit = 1 a tamper condition has been detected. in standalone mode the bit flag is also available in the sdatd pin. 7.10 phase compensation the STPM10 does not introduce any phase shift between the voltage and current channel. however, the voltage and current signals come from transducers, which could have inherent phase errors. for example, a phase error of 0.1 to 0.3 is not uncommon for a current transformer (ct). these phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. the errors associated with phase mismatch are particularly noticeable at low power factors. the STPM10 provides a means of digitally calibrating these small phase errors by introduc ing delays on the voltage or current signal. the amount of phase compensation can be set using the 4 bits of the phase calibration register (cph). the default value of this register is at a value of 0, which gives 0 phase compensation. when the 4 bits give a cph of 15 (1111) the compensation introduced is +0.576. this compensates the phase shift usually introduced by the current sensor, while the voltage sensor, normally a resistor divider, does not introduce any delay. the resolution step of the phase compensation is 0.038. 7.11 clock generator all the internal timing of the STPM10 is based on the clkout signal. this signal can be generated in three different ways: figure 19. timings of tamper module - secondary channel selected
STPM10 theory of operation doc id 17728 rev 3 23/51 1. rc: this oscillator mode can be selected us ing the rc configuration bit. if rc = 1, the STPM10 runs using the rc oscillator. a resistor connected between clkin and ground sets the rc current. for 4 mhz operation, the recommended settling resistor is 12 k . the oscillator frequency can be compens ated using the crc configuration bit. 2. quartz: if rc = 0, the oscillator works with an external crys tal. the recommended circuit is depicted in figure 20 (b). 3. external clock: by keeping rc=0, it is also possible to feed the clkout pin with an external oscillator signal. the clock generator is powered from an analog supply and is responsible for two tasks. the first is to retard the turn-on of some function blocks after por in order to help smooth the start of the external power supply circuitry by keeping off all major loads. the second task of the clock generator is to provide all necessary clocks for the analog and digital parts. during this task, the mdiv configuration bit is us ed to inform the device about the nominal frequency value of clkout. two nominal frequency ranges are expected to be from 4.000 mhz to 4.194 mhz (mdiv = 0) or from 8.000 mhz to 8.192 mhz (mdiv = 1). 7.11.1 rc startup procedure to use the device with rc oscillator the configuration bit rc (see ta bl e 1 1 ) must be set. since the default configuration is for a crystal oscillator, when a rc oscillator is used instead and the device is supplied for the very first time it is not internally clocked and consequently the dsp is inactive. in this condition it is not possible to set rc or any other configuration bit. the following spi procedure can be run in order to set the rc bit and provide the clock to the device: set the mode signal bank; perform a software reset; read the registers: bank mode signal should be checked and the records should show something (not 000000f0); clear the mode signal bank; do not perform a reading, and write configuration bit rc; in this way the rc oscillator is started. if the registers are read again, it can be seen that rc bit is set and bank is cleared. once the rc startup procedure is complete, the device is clocked and active. for details on mode signals refer to chapter 7.18 , for spi operations refer to chapter 7.19 . figure 20. different oscillator circuits with (a) quartz, (b) internal oscillator, (c) external source
theory of operation STPM10 24/51 doc id 17728 rev 3 7.12 resetting the STPM10 the STPM10 has no reset pin. the device is automatically reset by the por circuit when the v cc crosses the 2.5 v value, but it can also be reset through the spi interface by providing a dedicated command (see section 7.19 for remote reset command details). in case of reset caused by the por circuit, all clocks and both dc buffers in the analog part are kept off for about 30 ms, as well as all blocks of the digital part, except for the spi interface, which is held in a reset state for about 125 ms after a reset condition. when a reset is performed through spi, no delayed turn-on is generated. resetting the STPM10 causes all the functional modules of the STPM10 to be cleared, including the volatile memory. the reset through spi (remote reset request) normally takes place during production testing. 7.13 using the STPM10 in mi crocontroller-based meters the STPM10 can be used in microcontroller-based energy meters. the spi pins (scs, scl, sda, syn) are used for communication purposes, allowing the microcontroller to write and read the internal STPM10 registers. the zero-crossing signal is available at the zcr pin (see section 7.4 for details about the zcr signal). the wdg pin provides the watchdog signal (dog). the dog signal generates a 16 ms long positive pulse every 1.6 seconds. generation of these pulses can be suspended if data are read in intervals shorter than 1.6 s. the dog signal is actually a watchdog reset signal which can be used to control operation of an on-board microcontroller. it is set to high whenever the vdda voltage is below 2.5 v, but after vdda goes above 2.5 v this signal starts running. it is expected that an application microcontroller should access the data in the metering device on a regular basis at least 1/s (recommen ded is 32/s). every latching of results in the metering device requested from the microcontroller also resets the watchdog. if latching requests are not 1.6 seconds from one another, an active high pulse on wdg is produced, because the device assumes that the microcontroller is not operating properly. an application can use this signal either to control the reset pin of its microcontroller, or it can be tied to an interrupt pin. the latter option is recommended for a battery-backup application which can enter a sleep mode due to power-down conditions, and should not be reset by a metering device as it would exit from sleep mode. 7.14 energy to frequency conversion the STPM10 provides energy to frequency conversion both for calibration and energy readout purposes. in fact, one convenient way to verify the meter calibration is to provide a pulse train signal with 50% duty cycle whose fre quency signal is proportional to the active energy under steady load conditions. in this case, the user chooses a certain number of pulses on the led pin that correspond to 1 kwh. this value is called p. let us consider the case in which the led pin is configured to be driven from internal signal aw (active energy) whose frequency is proportional to the active energy. the signal aw is
STPM10 theory of operation doc id 17728 rev 3 25/51 taken from the 11 th bit of the active energy register, and consequently a relationship between the lsb value of the active energy register and the number of pulses provided per each kwh (p) can be defined as: equation 2 due to the innovative and proprietary power calculation algorithm, the frequency signal is not affected by any ripple at twice the line frequency. this feature strongly reduces the calibration time of the meter. in a practical example where the desired p is 64000 pulses/kwh (=17.7 hz*kw), we have: equation 3 k aw =7.63*10-6 wh this means that the reading of 0x00001 in the active energy register represents 7.63 wh, while 0xfffff represents 8 wh. the led pin can be driven from aw (active energy wide band), af (active energy limited at fundamental), rw (reactive energy) or sw (apparent energy) according to the value of the kmot bit. in this case, since the led pin is driven by signals different from that of aw, some other relationship between the lsb of the register and the number of pulses per kwh provided by the meter (p) must be defined: equation 4 k af = 4*k aw [wh] k rw = 2*k aw [varh] k sw = k aw [vah] table 9. led pin configuration kmot (2 bits) signal available on led pin # of pulses 0 aw type0* p [kwh] 1 af type1* p [kwh] 2 rw p [kvarh] 3 sw p [kvah] [] wh p 2 1000 k 11 aw ? =
theory of operation STPM10 26/51 doc id 17728 rev 3 7.15 status bits the STPM10 includes 8 status bits which provid e information about the current status of the meter. the status bits are the following: all these signal can be read through the spi interface. see section 7.15: status bits for details on the status bit location in the STPM10 data records. table 10. status bit description bit # name description condition 0 bil no-load condition bil = 0: no-load condition not detected bil = 1: no-load condition detected 1bcf signals status bcf = 0: signals active bcf = 1: one or both signals are stacked 2 bfr line frequency range bfr = 0: line frequency within the 45 hz - 65 hz range bfr = 1: line frequency out of range 3 bit tamper condition bit = 0: tamper not detected bit = 1: tamper detected 4 mux current channel selection mux = 0: primary current chann els selected by the tamper module mux = 1: secondary current channels selected by the tamper module 5 lin trend of the line voltage lin = 0: line voltage going from the minimum to the maximum value. (dv/dt > 0) lin = 1: line voltage going from the maximum to the minimum value. (dv/dt < 0) 6 pin output pin check pin = 0: output pins are consistent with the data pin = 1: output pins are different with the data, this means an output pin is forced to 1 or 0 7 hlt data validity hlt = 0: data records reading are valid. hlt = 1: data records are no t valid. a reset occurred and a restart is in progress
STPM10 theory of operation doc id 17728 rev 3 27/51 7.16 programming the STPM10 7.16.1 data records the STPM10 has 8 internal data record regist ers. every data record consists of a 4-bit parity code and 28-bit data value where the pari ty code is computed from the data value, which makes a total of 32 bits, or 4 bytes. figure 21 shows the data record structure with the name of the contained information. each bit of parity nibble is defined as odd parity of all seven corresponding bits of data nibbles. the first 6 registers are read-only, except for the 8-bit mode signals in the dfp register (the mode signals are described later in this paragraph). the last two registers are cfl and cfh. 7.17 configuration bits all the configuration bits that control the oper ation of the device (cfl and cfh data records) can be written in a temporary way. the configuration bit values are written in the so-called volatile memory, which are simple latches that hold the configuration data until the power is on or until a reset condition occurs (both por and remote reset). as indicated in the data records table, the configuration bits are 56. figure 21. STPM10 data records map upper f(u) 0 1 mode signals p p irms urms imom umom 1bit 1bit 1bit 20 bit 20 bit 8 bit 6 bit 11 bit 16 bit dap drp dsp cfh dfp dev dmv cfl reactive energy type0 active energy apparent energy type 1 energy lower part of configurators upper part of configurators status lower f(u) parity parity parity parity parity parity parity parity 4 bit msb lsb
theory of operation STPM10 28/51 doc id 17728 rev 3 each configuration bit can be written by sending a byte command to STPM10 through its spi interface. the procedure to write th e configuration bits is described in section 7.19: spi interface . table 11. configuration bit map address name n. of bits description (1) 6-bit binary dec 000000 0 - 1 reserved 000001 1 mdiv 1 measurement frequency range selection: - mdiv=0: 4.000 mhz to 4.194 mhz - mdiv=1: 8.000 mhz to 8.192 mhz 000010 2 rc 1 type of internal oscillator selection: - rc=0:crystal oscillator, - rc=1:rc oscillator 000011 3 - 1 reserved 000100 4 - 1 reserved 000101 5 pst 1 current channel sensor type and gain: if tmp=0 pst=0: primary is ct x8, secondary is not used, no tamper pst=1: primary is shunt x32, secondary is not used, no tamper if tmp=1 pst=0: primary is ct x8, secondary is ct x8, tamper pst=1: primary is ct x8, secondary is shunt x32, tamper 000110 6 - 1 reserved 000111 7 tmp 1 tamper enable 001000 8 frs 1 power calculation when bfr=1 - frs=0: energy accumulation is frozen, power is set to zero; - frs=1: normal energy accumulation and power computation (p=u*i); 001001 9 msbf 1 bit sequence output during record data reading selection: - msbf=0: msb first - msbf=1: lsb first 001010 10 fund 1 this bit swaps the information stored in t he type0 (first 20 bits of dap register) and type1 (first 20 bits of dfp register) active energy. - fund = 0: type 0 contains wide-band active energy, type1 contains fundamental active energy - fund = 1: type 0 contains fundamental active energy, type1 contains wide- band active energy 001100 12 lt c h 2 no-load condition threshold as product between v rms and i rms : ltch=0 800 ltch=1 1600 ltch=2 3200 ltch=3 6400 001101 13 (1) 001110 14 kmot 2 selection of pulses for led: kmot=0 type 0 active energy kmot=1 type 1 active energy kmot=2 reactive energy kmot=3 apparent energy 001111 15 (1)
STPM10 theory of operation doc id 17728 rev 3 29/51 010000 16 - 1 reserved 1 reserved 010001 17 - 010010 18 bgtc 2 band-gap temperature compensation bits. see figure 17 for details. 010011 19 (1) 010100 20 cph 4 4-bit unsigned data for compensation of phase error, 0+0.576. 16 values are possible with a compensati on step of 0.0384. when cph=0 the compensation is 0, when cph=15 the compensation is 0.576. 010101 21 010110 22 010111 23 (1) 011000 24 chv 8 8-bit unsigned data for voltage channel calibration. 256 values are possible. when chv is 0 the calibrator is at -12.5% of the nominal value. when chv is 255 the calibr ator is at +12.5%. the calibration step is then 0.098%. 011001 25 011010 26 011011 27 011100 28 011101 29 011110 30 011111 31 (1) 100000 32 chp 8 8-bit unsigned data for primary current channel calibration. 256 values are possible. when chp is 0 the calibrator is at -12.5% of the nominal value. when chp is 255 the calibr ator is at +12.5%. the calibration step is then 0.098%. 100001 33 100010 34 100011 35 100100 36 100101 37 100110 38 100111 39 (1) 101000 40 chs 8 8-bit unsigned data for secondary current channel calibration. 256 values are possible. when chs is 0 the calibrator is at -12.5% of the nominal value. when chs is 255 the calibr ator is at +12.5%. the calibration step is then 0.098%. 101001 41 101010 42 101011 43 101100 44 101101 45 101110 46 101111 47 (1) table 11. configuration bit map (continued) address name n. of bits description (1) 6-bit binary dec
theory of operation STPM10 30/51 doc id 17728 rev 3 as indicated above, the STPM10 includes 56 cfg bits. the cfg bits are not retained when the STPM10 supply is not available and they are cleared when a por occurs, but they are not cleared when a remote reset command (rrr) is sent through spi. normally, some of these bits must be loaded during power-up of the application. from the microcontroller, it could also reload the conf iguration and calibration values after power-on restart. 7.18 mode signals the STPM10 includes 8 mode signals located in the dfp data record. 3 of these are used only for internal testing purposes while 5 are us eful to change some of the operations of the STPM10. the mode signals are not retained when the STPM10 supply is not available and they are cleared when a por occurs, but they are not cleared when a remote reset command (rrr) is sent through spi. the mode signals bit can be written using the normal writing procedure of the spi interface (see section 7.19 ). 110000 48 crc 2 2-bit unsigned data for calibration of rc oscillator. (see ta bl e 5 ) crc=0, or crc=3 cal=0% crc=1, cal=+10%; crc=2, cal=-10%. 110001 49 (1) 110010 50 - 1 reserved 110011 51 - 1 reserved 110100 52 - 1 reserved 110101 53 crit 1 selection of tamper threshold: crit=0: 12,5% / crit=1: 6,25% 110110 54 - 1 reserved 110111 55 - 1 reserved (always set to 1 after production testing of die) 1. important: this bit represents the msb of the decimal value indicated in the description column. table 11. configuration bit map (continued) address name n. of bits description (1) 6-bit binary dec table 12. mode signal description bit # signal name bit value status binary command hex command 0 bank 0 used for rc startup procedure 0111000x 70 or 71 1 1111000x f0 or f1 1 reserved 2 reserved 3 reserved
STPM10 theory of operation doc id 17728 rev 3 31/51 ? csel: in normal operation, if the anti-tamper module is not activated (see pst configuration bits) the STPM10 selects channel 1 as the source of current information. for debug or calibration purposes it is possible to select channel 2 as the source of the current channel signal when the tamper module is disabled. this is done by setting the csel mode bit. ? precharge: this command swaps the sequence of data records read, allowing the reading of the last four data records firs t, and the first four second. the reading sequence is 5, 6, 7, 8, 1, 2, 3, 4. un like the other mode signals, the precharge command is not retained inside the STPM10, but should be sent each time before the reading of the data records. ? bank : it is used to activa te rc oscillator (see chapter 7.11.1 ). 7.19 spi interface the spi interface supports a simple serial protocol, which is implemented to enable communication between some master system (microcontroller or pc) and the device. three tasks can be performed with this interface: ? remote resetting of the device ? reading data records ? writing the mode bits and the configuration bits four pins of the device are dedicated to this purpose: scs, syn, scl and sda. scs, syn and scl are all input pins, while sda can be input or output according to whether the spi is in write or read mode. a high-level signal for these pins means a voltage level higher than 0.75 x vcc, while a low-level signal means a voltage value lower than 0.25 x vcc. the internal registers are not directly accessible. instead, 32 bits of transmission latches are used to pre-load the data before being read or written to the internal registers. the condition in which scs, syn and scl inputs are set to high level determines the idle state of the spi interface, and no data transfer occurs. ? scs: enables spi operation when low. ? syn: operates different functions according to the status of the scs pin. when scs is low, the syn pin status selects if the spi is in read (syn = 1) or write mode (syn = 0). when the scs is high and syn is also high, the results of the input or output data are transferred to the transmission latches. ? scl: basically the clock pin of the spi interf ace. this pin function is also controlled by the scs status. if scs is low, scl is the input of the serial bit synchronization 4 csel 0 current channel 1 selected when tamper is disabled 0111 100x 78 or 79 1 current channel 2 selected when tamper is disabled 1111 100x f8 or f9 5 reserved 6 reserved 7 precharge 1 swap the 32-bit data record readings. from 1,2,3,4,5,6,7,8, to 5,6, 7,8,1,2,3,4 and vice-versa 1111111x ff table 12. mode signal description (continued)
theory of operation STPM10 32/51 doc id 17728 rev 3 clock signal. when scs is high, scl is also high, determining the idle state of the spi. ? sda: the data pin. if scs is low, the op eration of sda is dependent on the status of the syn pin. if syn is high, sda is the output of the serial bit data (read mode). if syn is low, sda is the input of the serial bit data signal (write mode). if scs is high, sda is the input of the idle signal. any pin above has an internal weak pull-up mechanism of nominal 15 a. this means that when a pin is not forced by external signals, the state of the pin is logic high. a high state of any input pin described above is considered an idle (not active) state. for the spi to operate correctly, the STPM10 must be correctly supplied as described in section 7.6: power supply . an idle state of the spi module is recognized when the signals of pins syn, scs, scl and sda are in a logic high state. any spi oper ation should start from this idle state. when scs is active (low), signal sdatd should change its state at trailing edge of signal sclnlc and the signal sdatd should be stable at next leading edge of signal sclnlc. the first valid bit of sdatd is always started with activation of signal sclnlc. 7.20 remote reset the timing diagram of this operation is shown in figure 22 . the time step can be as short as 30 ns. the internal reset signal is called rrr. unlike the por, the rrr signal does not cause the 30 ms delayed restart of the analog module, and the 120 ms delay in the restart of the digital module. this signal does not clear the mode signals. figure 22. timing for providing remote reset request (1) 1. all time intervals must be longer than 30 ns. t 7 t 8 is the reset time; this interval must be longer than 30 ns also. t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 1 0 scs syn sclnlc sdatd scs syn sclnlc sdatd
STPM10 theory of operation doc id 17728 rev 3 33/51 7.21 reading data records a microcontroller is able to read all me asurement results and all system signals (configuration, calibration, status, mode). again, the time step can be as short as 30 ns. there are two phases of reading, called latching and shifting. latching is used to sample results into tran smission latches. the transmission latches are the flip-flops that hold the data in the spi interf ace. this is done with the active pulse on syn when scs is idle. the length of the pulse on syn must be longer than 2 periods of the measurement clock, i.e. more than 500 ns at 4 mhz. the shifting starts when scs become active. in the beginning of this phase, another much shorter pulse (30 ns) on syn should be applied in order to ensure that an internal transmission serial clock counter is reset to ze ro. an alternative way is to extend the pulse on syn into the second phase of reading. afte r this reset is done, a 32 serial clocks-per- data record should be applied. up to 8 data records can be read this way. this procedure can be aborted at any time through deactivation of scs (see figure 24 ). the first read-out byte of the data record is the least significant byte (lsb) of the data value and, of course, the fourth byte is the most si gnificant byte (msb) of the data value. each byte can be further divided into a pair of 4-bit nibbles, referred to as the most and least significant nibble (msn, lsn). this division makes sense with the msb of the data value because its msn holds the parity code rather than useful data. the sequence of the data record during the re ad operation is fixed. normally, an application reads the 1st through the 6th data record; the 7th and 8th data record would be read only when it needs to fetch the configuration data. however, an application may apply a precharge command (see ta b l e 1 2 ) prior to the reading phase. this command forces the device to respond with the sequence 5th - 8th, 1st - 4th. such a change of sequence can be used to skip the first four data records. the timing diagram of the reading operation is shown in figure 24 . one can see the latching and beginning of the shifting phase of the first byte (0x5f) of the firs t data record, and the end of reading. also, both alternatives for resetting the internal transmission serial clock counter are shown in signal syn. figure 23. data record reconstruction
theory of operation STPM10 34/51 doc id 17728 rev 3 t 1 t 2 : latching phase. interval value > 2/f clk t 2 t 3 : data latched, spi idle. interval value > 30 ns t 3 t 4 : enable spi for read operation. interval value > 30 ns t 4 t 5 : serial clock counter is reset. interval value > 30 ns t 5 t 6 : spi reset and enabled for read operation. interval value > 30 ns t 7 : internal data transferred to sda t 8 : sda data is stable and can be read the system that reads the data record from the STPM10 should check the integrity of each data record. if the check fails, the reading should be repeated, but this time only the shifting should be applied. otherwise, new data would be latched into transmission latches and the one incorrectly read would be lost. normally, each byte is read out as the most significant bit (msb) fi rst. but this can be changed by setting the msbf configuration bit in the STPM10 cfl data record. if this is done, each byte is read out as the least significant bit (lsb) first. 7.22 writing procedure each writable bit (configuration and mode bits) has its own 6-bit absolute address. for the configuration bits, the 6-bit address value corresponds to its decimal value, while for the mode bits the addresses are the ones indicated in section 7.18: mode signals . in order to change the state of a latch, one must send a byte of data to the STPM10, which is the normal way to send data via spi. this byte consists of 1-bit data to be latched (msb), followed by the 6-bit address of the destination latch, followed by 1-bit don't care data (lsb), which makes a total of 8 bits of command byte. for example, if we want to set configuration bit 47 (part of the secondary current channel calibrator) to 0, we must convert the decimal 47 to its 6-bit binary value: 101111. the byte command is then composed as follows: figure 24. timing for data record reading t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 sclnlc sdatd syn scs 1st byte last bit of 32nd byte f(read) sclnlc sdatd syn scs 1st byte last bit of 32nd byte f(read)
STPM10 theory of operation doc id 17728 rev 3 35/51 1 bit data value+6-bits address+1 bit (0 or 1) as depicted in figure 25 . in this case the binary command is 01011111 (0x5f), which is the one depicted, or 01011110 (0x5e): t 1 t 2 (> 30 ns): spi out of idle state t 2 t 3 (> 30 ns): spi enabled for write operation t 3 : data value is placed in sda t 4 : sda value is stable and shifted into the device t 3 t 5 (> 10 s): writing clock period t 3 t 5 : 1 bit data value t 5 t 6 : 6 bit address of the destination latch t 6 t 7 : 1 bit exe command t 8 : end of spi writing t 9 : spi enters idle state the same procedure should be applied for the mode signals, but in this case the 6-bit address must be taken from ta b l e 1 2 . the lsb of the command is also called the exe bi t because instead of the data bit value, the corresponding serial clock pulse is used to generate the necessary latching signal. this way the writing mechanism does not need the me asurement clock in order to operate, which makes the operation of spi module of STPM10 completely independent from the rest of device logic except for the signal por. commands for changing system si gnals should be sent during active signals scs and syn, as shown in figure 25 . the syn must be put low in order to disable the sda output driver of the STPM10 and make the sda an input pin. a string of commands can be sent within one period of active scs and syn signals, or a command can be followed by reading the data record. however, in this case, the syn should be deactivated in order to enable the sda output driver, and a syn pulse should be applied before activation of the scs in order to latch the data. figure 25. timing for writing configuration and mode bits
theory of operation STPM10 36/51 doc id 17728 rev 3 7.22.1 interfacing the standard 3-wire spi with the STPM10 spi due to the fact that a 2-wire spi is implemented in the STPM10, it is clear that sending any command from a standard 3-wire spi would requ ire a 3-wire to 2-wire interface, which should produce a proper signal on sda from host signals sdi, sdo and syn. the need for a single-gate 3-state buffer could be avoided th rough an emulation of spi just to send some commands. on a microcontroller this would be done by performing the following steps: 1. disable the spi module 2. set the sdi pin, which is connected to sda as an output 3. activate syn first, and then scs 4. apply a new bit value to sdi, and activate scl 5. deactivate scl 6. repeat the previous two steps seven times to complete a one byte transfer 7. repeat the previous three steps for any remaining byte transfers 8. set the sdi pin as an input 9. deactivate scs and syn 10. enable the spi module in case of a precharge command (0xff), the emulation above is not necessary. due to the pull-up device on the sda pin of the STPM10, the processor needs to perform the following steps: 1. activate syn first in order to latch the results 2. after at least 1 s, activate scs 3. write one byte to the transmitter of spi (this produces 8 pulses on scl with sdi=1) 4. deactivate syn 5. optionally read the data records (the sequence of reading is altered) 6. deactivate scs 7.23 energy calculation algorithm within the STPM10, the computing section of the measured active power uses a completely new patented signal processing approach. this approach allows the device to reach high a level of performance in terms of accuracy. the signals, coming from the sensors, for t he instantaneous voltage are calculated as follows: equation 5 v(t) = v?sin t where v is the peak voltage and is related to the line frequency. the instantaneous current is calculated using: equation 6 i(t) = i ? sin ( t + ? )
STPM10 theory of operation doc id 17728 rev 3 37/51 where i is the peak current, is related to the line frequency and ? is the phase difference between voltage and current. 7.23.1 active power in the STPM10, after the pre-conditioning and the a/d conversion, the digital voltage signal (which is dynamically more stable with respect to the current signal) is processed by a differentiator stage which transforms: equation 7 v(t) v?(t) = dv/dt = v ? ? cos t ? [see figure 26 - 5] the resulting signal, together with the pr e-processed and digita lized current signal: equation 8 i(t) = i ? sin( t + ? ); [see figure 26 - 6] are then available for the calculation process. these digital signals are also provided to two additional stages, which then integrate of themselves, obtaining: equation 9 dv/dt v(t) = v ? sin t; [see figure 26 - 7] equation 10 i(t) [see figure 26 - 8] ) t cos( i dt ) t ( i ) t ( i ? + ? ? = ? =
theory of operation STPM10 38/51 doc id 17728 rev 3 at this point four signals are available. by combining (pairing) them by means of two multiplying stages, two results are obtained: equation 11 [see figure 26 - 9] equation 12 [see figure 26 - 10] after these two operations, another stage performs the subtraction between the results p 2 and p 1 and a division by 2, obtaining the active power: figure 26. active energy computation diagram 2 ) t 2 cos( i v 2 cos i v dt ) t ( i dt dv ) t ( p 1 ? + ? ? ? ? ? ? ? = ? ? = / 2 ) t 2 cos( i v 2 cos i v ) t ( i ) t ( v ) t ( p 2 ? + ? ? ? ? ? ? = ? = /
STPM10 theory of operation doc id 17728 rev 3 39/51 equation 13 [see figure 26 - 11] in this way, the ac part v?i?cos(2 t + ? )/2 has been removed from the instantaneous power. the absence of any ac component allows for a very fast calibration procedure. it requires only the setting of (using the internal device programming registers) the voltage and current sensor conversion constants, using the effective voltage and current (v rms , i rms ) readings provided by the device?s built-in communication port, avoiding the time-averaged readings of the active power or the need for line synchronization. 7.23.2 reactive power the reactive power is produced using the prev iously-computed signals. in case of shunt sensor the voltage signal is derived while the current signal is not. a first computation is to multiply the ds value of the integrated voltage channel with the value of the integrated current channel, which yields: equation 14 the second is to multiply the filtered ds value of the voltage channel with the value of the filtered current channel: equation 15 from the above results, q1(t) is proportional to 1/ , while q2(t) is proportional to . the correct reactive power would result from the following formula: equation 16 since the above computation would need significant additional circuitry, the reactive power in the STPM10 is calculated usin g only the q1(t) multiplied by , which means: equation 17 2 cos i v 2 )) t ( p ) t ( p ( ) t ( p 1 2 ? ? ? = / ? / = () ) t 2 sin( sin 2 vi t cos( i ) t sin v ( ) t ( i ) t ( v ) t ( i dt ) t ( v ) t ( q 1 ? + ? ? ? = ? ? ? ? ? ? ? + ? ? = ? = ? = () ) t 2 sin( sin 2 vi ) t sin( i t cos v ) t ( i ) t ( v ) t ( q 2 ? + + ? ? ? = ? + ? = ? = ? = ? + ? ? = sin 2 vi 1 ) t ( q ) t ( q 2 1 q 2 1
theory of operation STPM10 40/51 doc id 17728 rev 3 the reactive power, then, presents a ripple at twice the line frequency. since the average value of a sinusoid is 0, this ripple does not co ntribute to the reactive energy calculation over time. moreover, in the STPM10 the reactive po wer is not used for meter calibration or to generate the stepper pulses, so this ripple does not affect the overall system performance. 7.23.3 apparent power and rms values the rms values are calculated star ting from the following formulas: equation 18 multiplying equation 18 by , the i rms value is obtained: equation 19 the rms voltage value is obtained by: equation 20 for the apparent power, another value is produced: equation 21 multiplying equation 18 and equation 21 , the apparent power is produced: equation 22 () ) t 2 sin( sin 2 vi ) t ( q 2 1 ) t ( q 1 3 ? + ? ? ? = ? ? = 2 i dt ) t ( i t 1 t 0 2 ? = 2 i i rms = 2 v dt ) t ( v t 1 v t 0 2 rms = = 2 v dt ) t ( v t 1 t 0 2 ? =
STPM10 theory of operation doc id 17728 rev 3 41/51 the dsp then performs the integration of the computed powers into energies. these integrators are implemented as up/down counters and they can roll over. 20-bit output buses of the counters are assigned as the most signific ant part of the energy dat a records. it is the responsibility of an app lication to read the counters at le ast every second, to avoid missing any rollover. 7.24 STPM10 calibration energy meters based on the STPM10 device can be calibrated in a fast and simple way. the calibration is essentially based on the single calibration of the voltage and current channel considering their rms values rather than on the frequency of the output pulse signal. when the two channels are calibrated, all the other measurements are calibrated too. this allows the calibration to be performed in only one point, thereby shortening the production time of the meter. this procedure is possible due to the following key factors: the device comprises two independent meter channels for line voltage and current, respectively. each channel includes its own digital calibrator, to adjust the rms in the range of 12.5% in 256 steps, and a digital filter, to remove any signal dc component. none of the final results are subject to the calibration procedure because they are achieved from such corrected signals by mathematical modules implemented by hard- wired dsp. the device computes different kinds of energies: active, reactive and apparent. the active energy is produced without the 2nd harmonic of the line frequency. it also computes rms values of measured voltage and current. the device produces an energy output pulse signal, but information can also be read through the serial port interface (spi) and communication channel. the device has an embedded memory of 56 bits, used for configuration and calibration purposes. the values of these bits can be read, or they can be changed temporarily through the spi communication channel. let's consider the basic information needed to start the calibration procedure: the typical STPM10 parameters and constants are also known (see ta b l e 1 4 ). 2 vi 2 v 2 i s = ? ? ? = table 13. working point settings parameter value line rms voltage v n 230 v line rms current i n 5 a power sensitivity p led: p=128000 pulses/kwh shunt sensor k s 0.42 mv/a
theory of operation STPM10 42/51 doc id 17728 rev 3 as shown in ta b l e 1 4 , only analog parameters are the object of calibration because they introduce a certain error. voltage adc amplification a v is constant, while a i is chosen according to the sensors used. the calibration algorithm first calculates the volt age divider ratio and, as a final result, the correction parameters, called k v and k i , which applied to STPM10 voltage and current measures compensate the small tolerances of the analog components that affect energy calculation. since k v and k i calibration parameters are the decimal representation of the corresponding configuration bytes chv and chp or chs (respectively, the voltage channel, primary current channel and secondary current channel calibration bytes), at the end of calibration, chv and chp or chs (according to the current channel under calibration, primary or secondary, respectively) the bits' values are obtained. in the following procedure chv, chp and chs are indicated as c v and c i . through hard-wired formulas, k v and k i tune measured values varying from 0.75 to 1, in 256 steps, according to the value of c v and c i (from 0 to 255). to obtain the greatest correction dynamic, initially calibrators are set in the middle of the range, thus obtaining a calibration range of 12.5% per voltage or current channel: calibrator value k v = k i = 0.875 c i = c v = 128 in this way, it is possible to tune k v and k i to obtain a precise measurement: for example c v = 0 generates a correction factor of -12.5% (k v = 0.75) and c v = 255 determines a correction factor of +12.5% (k v = 1), and so on. based on the above, the following formulas relating to k v ,i and c v ,i are obtained: k v,i = (c v,i / 128) * 0.125 + 0.75 c v,i = 1024 * k v,i - 768 table 14. device constants parameter value tolerance internal reference voltage v bg 1.23 v 2% internal calculation frequency f m 2 23 hz 50 ppm amplification of voltage adc a v 4 1% amplification of current adc a i 8, 16, 24, 32 2% gain of differentiator g dif 0.6135 gain of integrator g int 0.815 gain of decimation filter g df 1.004 rms voltage record length b v 2 11 rms current record length b i 2 16 constant d ud 2 17
STPM10 theory of operation doc id 17728 rev 3 43/51 the calibration procedure outputs c v and c i values, which allow the above power sensitivity of the meter. this sensitivity is used to ca lculate target frequency at the led pin for nominal voltage and current values: x f = f * 64 with: f = pm * i n * v n / 3600000 from the values above and for both chosen amplification factor a i = 32 and initial calibration data, the following target values can be calculated: target rms reading for a given i n : x i = in * k s * a i * k i * g int * g df * g dif * b i / (v bg * 1000) = 1573 target rms reading for a given v n : x v = f * b v * b i * d ud / (f m * x i ) = 852 the output of the voltage divider is then: v div = (x v * v bg )/ (2 * g dif * a v * k v * g df * g int * b v )= 145.6 mv choosing r 2 = 500 (connected between v i and v ss ), the r 1 resistor (connected between v line and v ip ) value is obtained: r 1 = r 2 * (v n - v div ) / v div = 789.3 indicating, with i a and v a , the real readings on the STPM10 rms voltage and current registers, and with x i and x v ideal values of rms current and voltage readings already calculated, the final values for calibrators can be calculated as: x v = (k v * v a ) / 0.875 x i = (k i * i a ) / 0.875 if the computed final calibration data would fall out of the calibration data range, the energy meter should be recognized as bad, or the given presumptions and calculations above should be checked. otherwise, if the final data of the calibrators would be written into the energy meter, the rms readings should be very close to the target values i and v, and the frequency of the led output should be very close to the target value f.
application design STPM10 44/51 doc id 17728 rev 3 8 application design the choice of the external components in the transduction section of the application is a crucial point in the application design, affecting the precision and the resolution of the whole system. among the several considerations, a compromise has to be found between the following needs: 1. maximize the signal to noise ratio in the voltage channel, 2. choose the current to voltage conversion ra tio ks and the voltage divider ratio in a way that calibration can be achieved (please refer to an2299) 3. choose ks to take advantage of the whol e current dynamic range according to desired maximum current and resolution. to maximize the signal to noise ratio of the cu rrent channel the voltage divider resistors ratio should be as close as possible to those shown in ta b l e 1 5 . the figure 27 below shows a reference schematic for an application with the following properties: p = 64000 imp/kwh i nom = 5 a i max = 60 a. typical values for the current sensors sensitiv ity, also used in the reference schematic below, are shown in ta bl e 1 6 . note: if the device is used in configuration pst = 1, tmp = 1 (primary channel with ct, secondary channel with shunt), the shunt ks must always be equal to one fourth of the current transformer ks. additional considerations on the application design, suggestions for noise and crosstalk reduction can be found in the an2317. table 15. resistor divider ratio function component parameter value unit line voltage interface resistor divider r to r ratio v rms =230v 1650 v/v r to r ratio v rms =110v 830 table 16. current channel typical components function component parameter value unit line current interface current shunt current to voltage conversion ratio ks 0.425 mv/a current transformer 1.7 rogowsky coil 0.13
STPM10 application design doc id 17728 rev 3 45/51 figure 27. STPM10 reference schematic with one current transformer and one shunt 3 3(5.4 2 2 2 k 6 6 5 340- -/. -/0 3#3 6$$$ 633 6## 6/40 6$$! ))0 )). ,%$ 3$!4$ 3#,.,# #,+/54 #,+). 39. 6). 6)0 )). ))0 , m 40 # 0 7 9 -(z 2 k 2 - $ 2 k 2 k 7 , m # n 2 k $ 6 2 k & 2 2 2 k # . # m 2 - # . $ 2 k 2 2 2 - $ # . # m 2 k # . # m # . #4 %8 # m 2 2 . # 0 * #/.! 6/40 6$$! 6$$ 6$$ ".w
package mechanical data STPM10 46/51 doc id 17728 rev 3 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
STPM10 package mechanical data doc id 17728 rev 3 47/51 dim. mm. inch. min. typ. max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0. 8 1 1.05 0.0 3 1 0.0 39 0.041 b 0.1 9 0. 3 0 0.007 0.012 c0.0 9 0.20 0.004 0.007 9 d 6.4 6.5 6.6 0.252 0.256 0.260 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4. 3 4.4 4.4 8 0.16 9 0.17 3 0.176 e 0.65 b s c 0.0256 b s c k0 8 0 8 l 0.45 0.60 0.75 0.01 8 0.024 0.0 3 0 t ss op20 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 00 8 7225c
package mechanical data STPM10 48/51 doc id 17728 rev 3 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t 22.4 0. 88 2 ao 6. 8 7 0.26 8 0.276 bo 6. 9 7.1 0.272 0.2 8 0 ko 1.7 1. 9 0.067 0.075 po 3 . 9 4.1 0.15 3 0.161 p 11. 9 12.1 0.46 8 0.476 tape & reel t ss op20 mechanical data
STPM10 package mechanical data doc id 17728 rev 3 49/51 figure 28. tssop20 footprint recommended data table 17. footprint data values mm. inch. a7.260.286 b4.930.194 c0.360.014 d0.650.025 e6.210.244
revision history STPM10 50/51 doc id 17728 rev 3 10 revision history table 18. document revision history date revision changes 31-aug-2010 1 initial release. 25-nov-2010 2 modified: table 5 on page 9 , 7.9: tamper detection module on page 20 . added: 7.11.1: rc startup procedure on page 23 and 8: application design on page 44 . 09-jun-2011 3 modified: table 5 on page 9 .
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